In the field of integrated circuit design, the IO (Input/Output) interface circuit is a circuit module used for realizing communication between chips.
When two or more chips are communicating with one another, the GPIO (General Purpose Input/Output) interface circuit is generally used for communication between chips. The GPIO interface circuit is characterized by being compatible with various voltages and transmission logics, which is usually compatible with voltages such as 1.2V/1.5V/1.8V/2.5V/3.3V and so on, and with transmission of CMOS (Complementary Metal Oxide Semiconductor) signals and LVDS (Low Voltage Differential Signaling) signals and so on.
The CMOS signal interface includes the single-end interface and the differential interface. The single-end interface transmits signals using a single wire connected with two terminals, which is characterized by defining data 0 or data 1 according to different signal voltages. As shown in FIG. 1, when a chip 1 communicates with a chip 2, a terminal A of an interface 101 is connected to a terminal B of an interface 201. When the terminal A transmits data 1 to the terminal B, it transmits a high level voltage to the terminal B; and when the terminal A transmits date 0 to the terminal B, it transmits a low level voltage to the terminal B. The differential interface transmits signals using two wires respectively connected with two pairs of terminals, which is characterized by defining data 0 or data 1 according to voltage difference between two terminals. As shown in FIG. 2, when the chip 1 communicates with the chip 2, terminals A+ and A− of an interface 102 are respectively connected to terminals B+ and B− of an interface 202. When the interface 102 transmits data 1 to the interface 102, the terminal A+ transmits a high level voltage to the terminal B+ and the terminal A− transmits a low level voltage to the terminal B−; and when the interface 102 transmits data 0 to the interface 102, the terminal A+ transmits a low level voltage to the terminal B+ and the terminal A− transmits a high level voltage to the terminal B−. Compared with the single-end interface, the differential interface has a better transmission performance and a higher transmission speed.
The LVDS interface is a high speed differential interface characterized by transmitting current signals via the interface and usually used for transmitting high speed data signals such as HD video signals.
The MIPI (Mobile Industry Processor Interface) is a low-voltage and low-power interface initiated by MIPI alliance, which is an open standard and specification for mobile application processors. As a mainstream high speed image transmission interface used in mobile devices, the MIPI has been widely used in various fields such as smartphones, tablet computers, wearable devices and virtual reality devices, etc.
The MIPI is also a differential interface, which defines data 0 or data 1 by voltage difference between two terminals. The MIPI includes HS Mode (High Speed mode) and LP Mode (Low Power mode). In HS Mode, the transmission speed can reach up to 500 MHz or even more. The definition of MIPI HS Mode of is shown in table 1 with the basis features of a transmit high level voltage ranging from 300 mV to 400 mV, a transmit low level voltage ranging from 0V to 100 mV, an average value of 200 mV between the high and low level voltages in standard condition, a fluctuation interval ranging from 150 mV to 250 mV for the average value, a voltage difference of 200 mV between the high and low level voltages in standard condition, and a fluctuation interval ranging from 140 mV to 270 mV for the voltage difference.
TABLE 1Definition of MIPI HS ModeParameterDescriptionMinNomMaxUnitsNotesVCMTXHS transmit static150200250mV1common-mode voltage|ΔVCMTX(1,0)|VCMTX mismatch when 5mV2output is Differential-1 or Differential-0|VOD|HS transmit differential 140200270mV1voltage|ΔVOD|VOD mismatch when 10mV2output is Differential-1 or Differential-0VOHHSHS output high voltage360mV1ZOSSingle ended output  40 5062.5ΩimpedenceΔZOSSingle ended output 10%impedance mismatch
The definition of MIPI LP Mode is shown in table 2, which defines the differential output interface LCMOS12 (the interface outputs a 1.2V differential voltage in form of CMOS logic).
TABLE 2Definition of MIPI LP ModeParameterDescriptionMinNomMaxUnitsNotesVOHThevenin output high level1.11.21.3VVOLThevenin ouput low level−5050mVZOLPOutput impedence of LP110Ω1, 2transmitter
FIG. 3 illustrates a signal diagram of the MIPI in HS Mode and LP Mode respectively. As shown in FIG. 3, the amplitude of the signal level ranges from 100 mV to 300 mV in HS Mode, and the amplitude of the signal level ranges from 0V to 1.2V in LP Mode.
With the rapid development of the mobile electronic devices, the MIPI is widely used as a new high speed interface for mobile devices. Especially, the MIPI output interface is widely used for image acquisition, transmission and display.
The existing MIPI output interfaces can be divided into two types. One type is a single MIPI output interface circuit as shown in FIG. 4, in which a single pair of MIPI circuits are designed in the chip and only used for transmission of MIPI signals. As shown in FIG. 5, the other type uses a differential output interface LVDS25E, a pair of differential output interface LVCMOS12 and off-chip resistors to emulate MIPI output transmission. In this solution, two pairs of interface circuits are used (one pair of LVDS25E output interfaces and one pair of LVCMOS12 differential output interfaces) so as to be compatible with MIPI outputs. However, the output speed of this solution is limited by LVDS25E output speed.
In conclusion, the existing single GPIO cannot be compatible with MIPI output interface in the prior art.